Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
48 Specification Update
• BTS/PEBS absolute maximum is less than a record size from the end of the
virtual address space
• The record that would cross BTS/PEBS absolute maximum will also continue
past the end of the virtual address space
A BTS/PEBS record can be written that will wrap at the 4G boundary (IA32) or 2^64
boundary (EM64T mode), and write memory outside of the BTS/PEBS buffer
Implication: Software that uses BTS/PEBS near the 4G boundary (IA32) or 2^64 boundary
(EM64T mode), and defines the buffer such that it does not hold an integer multiple
of records can update memory outside the BTS/PEBS buffer.
Workaround: Define BTS/PEBS buffer such that BTS/PEBS absolute maximum minus BTS/PEBS
buffer base is integer multiple of the corresponding record sizes as recommended in
the IA-32 Intel® Architecture Software Developers Manual, Volume 3.
Status: For the steppings affected, see the Summary Tables of Changes.
L60. Memory Ordering Failure May Occur with Snoop Filtering Third Party
Agents after Issuing and Completing a BWIL (Bus Write Invalidate
Line) or BLW (Bus Locked Write) Transaction
Problem: Under limited circumstances, the processors may, after issuing and completing a
BWIL or BLW transaction, retain data from the addressed cache line in shared state
even though the specification requires complete invalidation. This data retention may
also occur when a BWIL transaction’s self-snooping yields HITM snoop results.
Implication: A system may suffer memory ordering failures if its central agent incorporates
coherence sequencing which depends on full self-invalidation of the cache line
associated with (1) BWIL and BLW transactions, or (2) all HITM snoop results
without regard to the transaction type and snoop results’ source.
Workaround: 1. The central agent can issue a bus cycle that causes a cache line to be
invalidated (Bus Read Invalidate Line (BRIL) or BWIL transaction) in response to a
processor-generated BWIL (or BLW) transaction to ensure complete invalidation of
the associated cache line. If there are no intervening processor-originated
transactions to that cache line, the central agent’s invalidating snoop will get a clean
snoop result.