Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
Specification Update 49
Or
2. Snoop filtering central agents can:
a. Not use processor-originated BWIL or BLW transactions to update their
snoop filter information, or
b. Update the associated cache line state information to shared
state on the originating bus (rather than invalid state) in
reaction to a BWIL or BLW
Status: For the steppings affected, see the Summary Tables of Changes.
L61. Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS
Instruction with Fast Strings Enabled
Problem: Under limited circumstances while executing a REP MOVS/STOS string instruction,
with fast strings enabled, it is possible for the value in CR2 to be changed as a result
of an interim paging event, normally invisible to the user. Any higher priority
architectural event that arrives and is handled while the interim paging event is
occurring may see the modified value of CR2.
Implication: The value in CR2 is correct at the time that an architectural page fault is signaled.
Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
L62. TPR (Task Priority Register) Updates during Voltage Transitions of
Power Management Events May Cause a System Hang
Problem: Systems with Echo TPR Disable (R/W) bit (bit [23] of IA32_MISC_ENABLE register)
set to '0' (default), where xTPR messages are being transmitted on the system bus to
the processor, may experience a system hang during voltage transitions caused by
the power management events.
Implication: This may cause a system hang during voltage transitions of power management
events.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. The BIOS
workaround disables the Echo TPR updates on affected steppings.
Status: For the steppings affected, see the Summary Tables of Changes.
L63. It is Possible That Two specific Invalid Opcodes May Cause
Unexpected Memory Accesses