Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
50 Specification Update
Problem: A processor is expected to respond with an undefined opcode (#UD) fault when
executing either opcode 0F 78 or a Grp 6 Opcode with bits 5:3 of the Mod/RM field
set to 6, however the processor may respond instead, with a load to an incorrect
address.
Implication: This erratum may cause unpredictable system behavior or system hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
L64. VERR/VERW Instructions May Cause #GP Fault When Descriptor Is in
Non-canonical Space
Problem: If a descriptor referenced by the selector specified for the VERR or VERW instructions
is in non-canonical space, it may incorrectly cause a #GP fault on a processor
supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T).
Implication: Operating systems or drivers that reference a selector in non-canonical space may
experience an unexpected #GP fault. Intel has not observed this erratum with any
commercially available software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
L65. The Base of a Null Segment May Be Non-zero on a Processor
Supporting Intel® Extended Memory 64 Technology (Intel® EM64T)
Problem: In IA-32e mode of the Intel EM64T processor, the base of a null segment may be
non-zero.
Implication: Due to this erratum, Intel EM64T enabled systems may encounter unexpected
behavior when accessing memory using the null selector.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
L66. Upper 32 Bits of FS/GS with Null Base May Not Get Cleared in Virtual-
8086 Mode on Processors with Intel
®
Extended Memory 64
Technology (Intel
®
EM64T) Enabled