Intel Celeron D Processor 300 Sequence on 90 nm Process
Errata
Specification Update 51
Problem: For processors with Intel EM64T enabled, the upper 32 bits of the FS and GS data
segment registers corresponding to a null base may not get cleared when segments
are loaded in Virtual-8086 mode.
Implication: This erratum may cause incorrect data to be loaded or stored to memory if FS/GS is
not initialized before use in 64-bit mode. Intel has not observed this erratum with
any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
L67. Processor May Fault When the Upper 8 Bytes of Segment Selector Is
Loaded from a Far Jump through a Call Gate via the Local Descriptor
Table
Problem: In IA-32e mode of the Intel EM64T processor, control transfers through a call gate
via the Local Descriptor Table (LDT) that uses a 16-byte descriptor, the upper 8-byte
access may wrap and access an incorrect descriptor in the LDT. This only occurs on
an LDT with a LIMIT>0x10008 with a 16-byte descriptor that has a selector of
0xFFFC.
Implication: In the event this erratum occurs, the upper 8-byte access may wrap and access an
incorrect descriptor within the LDT, potentially resulting in a fault or system hang.
Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
L68. Loading a Stack Segment with a Selector that References a Non-
canonical Address Can Lead to a #SS Fault on a Processor Supporting
Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Problem: When a processor supporting Intel EM64T is in IA-32e mode, loading a stack
segment with a selector which references a non-canonical address will result in a #SS
fault instead of a #GP fault.
Implication: When this erratum occurs, Intel EM64T enabled systems may encounter unexpected
behavior.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.