Intel Celeron D Processor 300 Sequence on 90 nm Process

Errata
56 Specification Update
Implication: This erratum may cause loads to be observed out of order. Intel has not observed
this erratum with any commercially available software or system.
Workaround: Software should ensure at least one of the following is true when modifying
shared data by multiple agents:
• The shared data is aligned
• Proper semaphores or barriers are used in order to prevent concurrent data
accesses
Status: For the steppings affected, see the Summary Tables of Changes.
L80. The IA32_MC0_STATUS and IA32_MC1_STATUS Overflow Bit is not
set when Multiple Un-correctable Machine Check Errors Occur at the
Same Time
Problem: When two MC0/MC1 enabled un-correctable machine check errors are detected in the
same internal clock cycle, the highest priority error will be logged in
IA32_MC0_STATUS / IA32_MC1_STATUS register, but the overflow bit may not be
set.
Implication: The highest priority error will be logged and signaled if enabled, but the overflow bit
in the IA32_MC0_STATUS/ IA32_MC1_STATUS register may not be set.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
L81. Debug Status Register (DR6) Breakpoint Condition Detected Flags
May be set Incorrectly
Problem: The Debug Status Register (DR6) may report detection of a spurious breakpoint
condition under certain boundary conditions when either:
• A "MOV SS" or "POP SS" instruction is immediately followed by a hardware
debugger breakpoint instruction, or
• Any debug register access ("MOV DRx, r32" or "MOV r32, DRx") results in a
general-detect exception condition.
Implication: Due to this erratum the breakpoint condition detected flags may be set incorrectly.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
L82. A VM Exit Occurring in IA-32e Mode May Not Produce a VMX Abort
When Expected.
Problem: If a VM exit occurs while the processor is in IA-32e mode and the “host address-
space size” VM-exit control is 0, a VMX abort should occur. Due to this erratum, the
expected VMX aborts may not occur and instead the VM Exit will occur normally. The