Intel Celeron Processor in the 478-Pin Package Specification Update

Errata

42 Intel

Celeron

Processor in the 478-Pin Package Specification Update

AC62. With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked

FP Exception May Take Single Step Trap before Retirement of Instruction

Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for

external events to occur, including a transition to a lower power state. When resuming from the

lower power state, it may be possible to take the single step trap before the execution of the

original FP instruction completes.

Implication: A Single Step trap will be taken when not expected.

Workaround: None Identified.

Status: For the steppings affected, see the Summary Tables of Changes.

AC63. BTS (Branch Tree Store) and PEBS (Precise Event Based Sampling) May

Update Memory outside the BTS/PEBS Buffer

Problem: If the BTS/PEBS buffer is defined such that:

• The difference between BTS/PEBS buffer base and BTS/PEBS absolute maximum is

not an integer multiple of the corresponding record sizes

• BTS/PEBS absolute maximum is less than a record size from the end of the virtual

address space

• The record that would cross BTS/PEBS absolute maximum will also continue past the

end of the virtual address space

A BTS/PEBS record can be written that will wrap at the 4G boundary (IA32) or 2^64 boundary

(EMT64 mode), and write memory outside of the BTS/PEBS buffer.

Implication: Software that uses BTS/PEBS near the 4G boundary (IA32) or 2^64 boundary (EMT64 mode),

and defines the buffer such that it does not hold an integer multiple of records can update memory

outside the BTS/PEBS buffer.

Implication: A Single Step trap will be taken when not expected.

Workaround: Define BTS/PEBS buffer such that BTS/PEBS absolute maximum minus BTS/PEBS buffer base

is integer multiple of the corresponding record sizes as recommended in the Programmers

Reference Manual Volume 3.

Status: For the steppings affected, see the Summary Tables of Changes.

AC64. Memory Ordering Failure May Occur with Snoop Filtering Third-Party

Agents after Issuing and Completing a BWIL (Bus Write Invalidate Line) or

BLW (Bus Locked Write) Transaction

Problem: Under limited circumstances, the processors may, after issuing and completing a BWIL or BLW

transaction, retain data from the addressed cache line in shared state even though the specification

requires complete invalidation. This data retention may also occur when a BWIL transaction’s

self-snooping yields HITM snoop results.

Implication: A system may suffer memory ordering failures if its central agent incorporates coherence

sequencing which depends on full self-invalidation of the cache line associated with (1) BWIL