Specification Update

MOBILE INTEL

CELERON

PROCESSOR at 466 MHz, 433 MHz, 400 MHz,

366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE

H17. Built-in Self Test Always Gives Nonzero Result

Problem: The Built-in Self Test (BIST) of the Mobile Intel Celeron processor does not give a zero result to

indicate a passing test. Regardless of pass or fail status, bit 6 of the BIST result in the EAX register after

running BIST is set.

Implication:

Software which relies on a zero result to indicate a passing BIST will indicate BIST failure.

Workaround: Mask bit 6 of the BIST result register when analyzing BIST results.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

H18. Cache State Corruption in the Presence of Page A/D-bit

Setting and Snoop Traffic

Problem: If an operating system uses the Page Access and/or Dirty bit feature implemented in the Intel

architecture and there is a significant amount of snoop traffic on the bus, while the processor is setting the

Access and/or Dirty bit the processor may inappropriately change a single L1 cache line to the modified state.

Implication:

The occurrence of this erratum may result in cache incoherency, which may cause parity errors,

data corruption (with no parity error), unexpected application or operating system termination, or system hangs.

Workaround: It is possible for BIOS code to contain a workaround for this erratum.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

H19. Snoop Cycle Generates Spurious Machine Check Exception

Problem: The processor may incorrectly generate a Machine Check Exception (MCE) when it processes a

snoop access that does not hit the L1 data cache. Due to an internal logic error, this type of snoop cycle may

still check data parity on undriven data lines. The processor generates a spurious machine check exception as

a result of this unnecessary parity check.

Implication:

A spurious machine check exception may result in an unexpected system halt if Machine Check

Exception reporting is enabled in the operating system.

Workaround: It is possible for BIOS code to contain a workaround for this erratum. This workaround would fix

the erratum; however, the data parity error will still be reported.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

H20. MOVD/MOVQ Instruction Writes to Memory Prematurely

Problem: When an instruction encounters a fault, the faulting instruction should not modify any CPU or

system state. However, when the MMX™ technology store instructions MOVD and MOVQ encounter any of the

following events, it is possible for the store to be committed to memory even though it should be canceled:

1. If CR0.EM = 1 (Emulation bit), then the store could happen prior to the triggered invalid opcode exception.

2. If the floating-point Top-of-Stack (FP TOS) is not zero, then the store could happen prior to executing the

processor assist routine that sets the FP TOS to zero.