Specification Update

MOBILE INTEL

CELERON

PROCESSOR at 466 MHz, 433 MHz, 400 MHz,

366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE

1. Rather than using the MOVSX-MOVD or CBW-MOVD pairing to handle one variable at a time, use the sign

extension capabilities (PSRAW, etc.) within MMX technology for operating on multiple variables. This would

result in higher performance as well.

2. Insert another operation that modifies or copies the sign-extended value between the MOVSX/IMUL/CBW

instruction and the MOVD instruction as in the example below:

XOR EAX, EAX (or SUB EAX, EAX)

MOVSX AX, BL (or other MOVSX, other IMUL or CBW instruction)

*MOV EAX, EAX

MOVD MM0, EAX

*Note: MOV EAX, EAX is used here as it is fairly generic. Again, EAX can be any 32-bit register.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

H24. Premature Execution of a Load Operation Prior to Exception

Handler Invocation

Problem: This erratum can occur with any of the following situations:

1. If an instruction that performs a memory load causes a code segment limit violation

2. If a waiting floating-point instruction or MMX™ instruction that performs a memory load has a floating-point

exception pending

3. If an MMX instruction that performs a memory load and has either CR0.EM =1 (Emulation bit set), or a

floating-point Top-of-Stack (FP TOS) not equal to 0, or a DNA exception pending

If any of the above circumstances, occur it is possible that the load portion of the instruction will have executed

before the exception handler is entered.

Implication:

In normal code execution where the target of the load operation is to write back memory there is

no impact from the load being prematurely executed, nor from the restart and subsequent re-execution of that

instruction by the exception handler. If the target of the load is to uncached memory that has a system side-

effect, restarting the instruction may cause unexpected system behavior due to the repetition of the side-effect.

Workaround: Code which performs loads from memory that has side-effects can effectively workaround this

behavior by using simple integer-based load instructions when accessing side-effect memory and by ensuring

that all code is written such that a code segment limit violation cannot occur as a part of reading from side-effect

memory.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

H25. Read Portion of RMW Instruction May Execute Twice

Problem: When the Mobile Intel Celeron processor executes a read-modify-write (RMW) arithmetic

instruction, with memory as the destination, it is possible for a page fault to occur during the execution of the

store on the memory operand after the read operation has completed but before the write operation completes.

If the memory targeted for the instruction is UC (uncached), memory will observe the occurrence of the initial

load before the page fault handler and again if the instruction is restarted.

Implication:

This erratum has no effect if the memory targeted for the RMW instruction has no side-effects. If,

however, the load targets a memory region that has side-effects, multiple occurrences of the initial load may

lead to unpredictable system behavior.