Specification Update

MOBILE INTEL

CELERON

PROCESSOR at 466 MHz, 433 MHz, 400 MHz,

366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE

Workaround: Hardware and software developers who write device drivers for custom hardware that may

have a side-effect style of design should use simple loads and simple stores to transfer data to and from the

device. Then, the memory location will simply be read twice with no additional implications.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

H26. Intervening Writeback May Occur During Locked Transaction

Problem: During a transaction which has the LOCK# signal asserted (e.g., a locked transaction), there is a

potential for an explicit writeback caused by a previous transaction to complete while the bus is locked. The

explicit writeback will only be issued by the processor which has locked the bus, and the lock signal will not be

deasserted until the locked transaction completes, but the atomicity of a lock may be compromised by this

erratum. Note that the explicit writeback is an expected cycle, and no memory ordering violations will occur.

This erratum is, however, a violation of the bus lock protocol.

Implication:

A chipset or third-party agent (TPA) which tracks bus transactions in such a way that locked

transactions may only consist of a read-write or read-read-write-write locked sequence, with no transactions

intervening, may lose synchronization of state due to the intervening explicit writeback. Systems using chipsets

or TPAs which can accept the intervening transaction will not be affected.

Workaround: The bus tracking logic of all devices on the system bus should allow for the occurrence of an

intervening transaction during a locked transaction.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

H27. MC2_STATUS MSR Has Model-Specific Error Code and

Machine Check Architecture Error Code Reversed

Problem: The Intel Architecture Software Developer’s Manual, Volume 3: System Programming Guide,

documents that for the MCi_STATUS MSR, bits 15:0 contain the MCA (machine-check architecture) error code

field and bits 31:16 contain the model-specific error code field. However, for the MC2_STATUS MSR, these bits

have been reversed. For the MC2_STATUS MSR, bits 15:0 contain the model-specific error code field and bits

31:16 contain the MCA error code field.

Implication:

A machine check error may be decoded incorrectly if this erratum on the MC2_STATUS MSR is

not taken into account.

Workaround: When decoding the MC2_STATUS MSR, reverse the two error fields.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.