Specification Update

MOBILE INTEL
®
CELERON
®
PROCESSOR at 466 MHz, 433 MHz, 400 MHz,
366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE
28
H28. Mixed Cacheability of Lock Variables Is Problematic in MP
Systems
Problem: This errata only affects multiprocessor systems where a lock variable address is marked cacheable
in one processor and uncacheable in any others. The processors which have it marked uncacheable may stall
indefinitely when accessing the lock variable. The stall is only encountered if:
• One processor has the lock variable cached, and is attempting to execute a cache lock.
• The processor that has that address cached has it cached in its L2 only.
Other processors, meanwhile, issue back to back accesses to that same address on the bus.
Implication:
MP systems where all processors either use cache locks or consistent locks to uncacheable
space will not encounter this problem. If, however, a lock variable’s cacheability varies in different processors,
and several processors are all attempting to perform the lock simultaneously, an indefinite stall may be
experienced by the processors which have it marked uncacheable in locking the variable (if the conditions
above are satisfied). Intel has only encountered this problem in focus testing with artificially generated external
events. Intel has not currently identified any commercial software which exhibits this problem.
Workaround: Follow a homogenous model for the memory type range registers (MTRRs), ensuring that all
processors have the same cacheability attributes for each region of memory; do not use locks whose memory
type is cacheable on one processor, and uncacheable on others. Avoid page table aliasing, which may produce
a nonhomogenous memory model.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
H29. Thermal Sensor May Assert SMBALERT# Incorrectly
Problem: The Intel Celeron Processor Mobile Module has a thermal sensor that monitors the processor core’s
temperature. Please note that desktop systems could have a similar thermal device. The thermal sensor asserts
SMBALERT# if the processor temperature exceeds the temperature limits set in the Alarm Threshold Registers
(T
HIGH
, T
LOW
). It also sets the corresponding Status Register bits to identify the cause of the interrupt. Figure 1
gives one example of the how the SMBALERT# signal could be used in a system.