Specification Update

MOBILE INTEL

CELERON

PROCESSOR at 466 MHz, 433 MHz, 400 MHz,

366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE

H30. MOV With Debug Register Causes Debug Exception

Problem: When in V86 mode, if a MOV instruction is executed on debug registers, a general-protection

exception (#GP) should be generated, as documented in the Intel Architecture Software Developer's Manual,

Volume 3: System Programming Guide, Section 15.2. However, in the case when the general detect enable flag

(GD) bit is set, the observed behavior is that a debug exception (#DB) is generated instead.

Implication:

With debug-register protection enabled (e.g., the GD bit set), when attempting to execute a MOV

on debug registers in V86 mode, a debug exception will be generated instead of the expected general-

protection fault.

Workaround: In general, operating systems do not set the GD bit when they are in V86 mode. The GD bit is

generally set and used by debuggers. The debug exception handler should check that the exception did not

occur in V86 mode before continuing. If the exception did occur in V86 mode, the exception may be directed to

the general-protection exception handler.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

H31. Upper Four PAT Entries Not Usable With Mode B or Mode C

Paging

Problem: The Page Attribute Table (PAT) contains eight entries, which must all be initialized and considered

when setting up memory types for the Mobile Intel Celeron processor. However, in Mode B or Mode C paging,

the upper four entries do not function correctly for 4-Kbyte pages. Specifically, bit seven of page table entries

that translate addresses to 4-Kbyte pages should be used as the upper bit of a three-bit index to determine the

PAT entry that specifies the memory type for the page. When Mode B (CR4.PSE = 1) and/or Mode C

(CR4.PAE) are enabled, the processor forces this bit to zero when determining the memory type regardless of

the value in the page table entry. The upper four entries of the PAT function correctly for 2-Mbyte and 4-Mbyte

large pages (specified by bit 12 of the page directory entry for those translations).

Implication:

Only the lower four PAT entries are useful for 4KB translations when Mode B or C paging is

used. In Mode A paging (4-Kbyte pages only), all eight entries may be used. All eight entries may be used for

large pages in Mode B or C paging.

Workaround: None identified

Status: For the steppings affected see the Summary of Changes at the beginning of this section.