Specification Update

MOBILE INTEL
®
CELERON
®
PROCESSOR at 466 MHz, 433 MHz, 400 MHz,
366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE
33
H32. Incorrect Memory Type May be Used When MTRRs Are
Disabled
Problem: If the Memory Type Range Registers (MTRRs) are disabled without setting the CR0.CD bit to
disable caching, and the Page Attribute Table (PAT) entries are left in their default setting, which includes
UC- memory type (PCD = 1, PWT = 0; see the Intel Architecture Software Developer’s Manual, Volume 3:
System Programming Guide, for details), data for entries set to UC- will be cached as if the memory type were
writeback (WB). Also, if the page tables are set to a memory type other than UC-, then the effective memory
type used will be that specified by the page tables and PAT. Any regions of memory normally forced to UC by
the MTRRs (such as the VGA video region) may now be incorrectly cached and speculatively accessed.
Even if the CR0.CD bit is correctly set when the MTRRs are disabled and the PAT is left in its default state, then
retries and out of order retirement of UC accesses may occur, contrary to the strong ordering expected for
these transactions.
Implication:
The occurrence of this erratum may result in the use of incorrect data and unpredictable
processor behavior when running with the MTRRs disabled. Interaction between the mouse, cursor, and VGA
video display leading to video corruption may occur as a symptom of this erratum as well.
Workaround: Ensure that when the MTRRs are disabled, the CR0.CD bit is set to disable caching. This
recommendation is described in the Intel Architecture Software Developer’s Manual, Volume 3: System
Programming Guide. If it is necessary to disable the MTRRs, first clear the PAT register before setting the
CR0.CD bit, flushing the caches, and disabling the MTRRs to ensure that UC memory type is always returned
and strong ordering is maintained.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
H33. Misprediction in Program Flow May Cause Unexpected
Instruction Execution
Problem: To optimize performance through dynamic execution technology, the P6 architecture has the ability
to predict program flow. In the event of a misprediction, the processor will normally clear the incorrect
prediction, adjust the EIP to the correct location, and flush out any instructions it may have fetched from the
misprediction. In circumstances where a branch misprediction occurs, the correct target of the branch has
already been opportunistically fetched into the streaming buffers, and the L2 cycle caused by the evicted cache
line is retried by the L2 cache, the processor may fail to flush out the retirement unit before the speculative
program flow is committed to a permanent state.
Implication:
The results of this erratum may range from no effect to unpredictable application or OS failure.
Manifestations of this failure may result in:
• Unexpected values in EIP
• Faults or traps (e.g., page faults) on instructions that do not normally cause faults
• Faults in the middle of instructions
• Unexplained values in registers/memory at the correct EIP
Workaround: It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.