Specification Update

MOBILE INTEL
®
CELERON
®
PROCESSOR at 466 MHz, 433 MHz, 400 MHz,
366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE
34
H34. Data Breakpoint Exception in a Displacement Relative Near
Call May Corrupt EIP
Problem: If a misaligned data breakpoint is programmed to the same cache line as the memory
location where the stack push of a near call is performed and any data breakpoints are enabled,
the processor will update the stack and ESP appropriately, but may skip the code at the destination
of the call. Hence, program execution will continue with the next instruction immediately following
the call, instead of the target of the call.
Implication: The failure mechanism for this erratum is that the call would not be taken; therefore,
instructions in the called subroutine would not be executed. As a result, any code relying on the
execution of the subroutine will behave unpredictably.
Workaround: Whether enabled or not, do not program a misaligned data breakpoint to the same
cache line on the stack where the push for the near call is performed.
Status: For the stepping affected see the Summary of Changes at the beginning of this section.
H35. System Bus ECC Not Functional With 2:1 Ratio
Problem: If a processor is underclocked at a core frequency to system bus frequency ratio of 2:1 and system
bus ECC is enabled, the system bus ECC detection and correction will negatively affect internal timing
dependencies.
Implication: If system bus ECC is enabled, and the processor is underclocked at a 2:1 ratio, the system may
behave unpredictably due to these timing dependencies.
Workaround: All bus agents that support system bus ECC must disable it when a 2:1 ratio is used.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
H36. Fault on REP CMPS/SCAS Operation May Cause Incorrect
EIP
Problem: If either a General Protection Fault, Alignment Check Fault or Machine Check Exception occur
during the first iteration of a REP CMPS or a REP SCAS instruction, an incorrect EIP may be pushed onto the
stack of the event handler if all the following conditions are true:
• The event occurs on the initial load performed by the instruction(s)
• The condition of the zero flag before the repeat instruction happens to be opposite of the repeat condition
(e.g., REP/REPE/REPZ CMPS/SCAS with ZF = 0 or RENE/REPNZ CMPS/SCAS with ZF = 1)
• The faulting micro-op and a particular micro-op of the REP instruction are retired in the retirement unit in a
specific sequence
The EIP will point to the instruction following the REP CMPS/SCAS instead of pointing to the faulting instruction.
Implication: The result of the incorrect EIP may range from no effect to unexpected application/OS behavior.
Workaround: None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this section.