Specification Update

MOBILE INTEL

CELERON

PROCESSOR at 466 MHz, 433 MHz, 400 MHz,

366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE

H37. RDMSR or WRMSR To Invalid MSR Address May Not Cause

GP Fault

Problem: The RDMSR and WRMSR instructions allow reading or writing of MSRs (Model Specific Registers)

based on the index number placed in ECX. The processor should reject access to any reserved or

unimplemented MSRs by generating #GP(0). However, there are some invalid MSR addresses for which the

processor will not generate #GP(0).

Implication: For RDMSR, undefined values will be read into EDX:EAX. For WRMSR, undefined processor

behavior may result.

Workaround: Do not use invalid MSR addresses with RDMSR or WRMSR.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

H38. SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null

Segment Selector” to SS and CS Registers

Problem: According to the processor specification, attempting to load a null segment selector into the CS and

SS segment registers should generate a General Protection Fault (#GP). Although loading a null segment

selector to the other segment registers is allowed, the processor will generate an exception when the segment

However, the SYSENTER instruction can implicitly load a null value to the SS segment selector. This can occur

if the value in SYSENTER_CS_MSR is between FFF8h and FFFBh when the SYSENTER instruction is

executed. This behavior is part of the SYSENTER/SYSEXIT instruction definition; the content of the

SYSTEM_CS_MSR is always incremented by 8 before it is loaded into the SS. This operation will set the null bit

in the segment selector if a null result is generated, but it does not generate a #GP on the SYSENTER

instruction itself. An exception will be generated as expected when the SS register is used to access memory,

however.

The SYSEXIT instruction will also exhibit this behavior for both CS and SS when executed with the value in

SYSENTER_CS_MSR between FFF0h and FFF3h, or between FFE8h and FFEBh, inclusive.

Implication: These instructions are intended for operating system use. If this erratum occurs (and the OS

does not ensure that the processor never has a null segment selector in the SS or CS segment registers), the

processor’s behavior may become unpredictable, possibly resulting in system failure.

Workaround: Do not initialize the SYSTEM_CS_MSR with the values between FFF8h and FFFBh, FFF0h

and FFF3h, or FFE8h and FFEBh before executing SYSENTER or SYSEXIT.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.