Specification Update

MOBILE INTEL

CELERON

PROCESSOR at 466 MHz, 433 MHz, 400 MHz,

366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE

H39. PRELOAD Followed by EXTEST Does Not Load Boundary

Scan Data

Problem: According to the IEEE 1149.1 Standard, the EXTEST instruction would use data “typically loaded

onto the latched parallel outputs of boundary-scan shift-register stages using the SAMPLE/PRELOAD

instruction prior to the selection of the EXTEST instruction.” As a result of this erratum, this method cannot be

used to load the data onto the outputs.

Implication: Using the PRELOAD instruction prior to the EXTEST instruction will not produce expected data

after the completion of EXTEST.

Workaround: None identified

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

H40. Far Jump to New TSS With D-bit Cleared May Cause System

Hang

Problem: A task switch may be performed by executing a far jump through a task gate or to a new Task State

Segment (TSS) directly. Normally, when such a jump to a new TSS occurs, the D-bit (which indicates that the

page referenced by a Page Table Entry (PTE) has been modified) for the PTE which maps the location of the

previous TSS will already be set and the processor will operate as expected. However, if the D-bit is clear at the

time of the jump to the new TSS, the processor will hang.

Implication: If an OS is used which can clear the D-bit for system pages, and which jumps to a new TSS on a

task switch, then a condition may occur which results in a system hang. Intel has not identified any commercial

software which may encounter this condition; this erratum was discovered in a focused testing environment.

Workaround: Ensure that OS code does not clear the D-bit for system pages (including any pages that

contain a task gate or TSS). Use task gates rather than jumping to a new TSS when performing a task switch.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

H41. Incorrect Chunk Ordering May Prevent Execution of the

Machine Check Exception Handler After BINIT#

Problem: If a catastrophic bus error is detected which results in a BINIT# assertion, and the BINIT# assertion

is propagated to the processor’s L2 cache at the same time that data is being sent to the processor, then the

data may become corrupted in the processor’s L1 cache.

Implication: Since BINIT# assertion is due to a catastrophic event on the bus, the corrupted data will not be

used. However, it may prevent the processor from executing the Machine Check Exception (MCE) handler,

causing the system to hang.

Workaround: None identified

Status: For the steppings affected see the Summary of Changes at the beginning of this section.