Specification Update

MOBILE INTEL

CELERON

PROCESSOR at 466 MHz, 433 MHz, 400 MHz,

366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE

H42. Resume Flag May Not Be Cleared After Debug Exception

Problem: The Resume Flag (RF) is normally cleared by the processor after executing an instruction which

causes a debug exception (#DB). In the process of determining whether the RF needs to be cleared after

executing the instruction, the processor uses an internal register containing stale data. The stale data may

unpredictably prevent the processor from clearing the RF.

Implication: If this erratum occurs, further debug exceptions will be disabled.

Workaround: None identified

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

H43. Processor May Return Invalid Parameters on Execution of

the CPUID Instruction

Problem: The Mobile Module based Intel Celeron processor with on-die L2 cache may return an incorrect

"Maximum CPUID Input Value.” The Mobile Module based Intel Celeron processor with on-die L2 cache is

specified to return a value of 2 in the EAX register when the CPUID instruction is executed with EAX=0;

however, this erratum may result in the value of 3 being returned in EAX. It is also possible that bit 18 of the

EDX register will be set to a 1 when CPUID is executed with EAX=1. This bit is defined as reserved for the

Mobile Module based Intel Celeron processor with on-die L2 cache, but is expected to be set to zero. If CPUID

were to be executed on the Mobile Module based Intel Celeron processor with on-die L2 cache with EAX=3 the

processor should return the cache parameters in the integer registers (EAX, EBX, ECX, EDX); however, the

processors affected by this erratum will return undefined values in the integer registers.

Implication: Intel has not seen any software failures as a result of this erratum; however, since software

written for the Mobile Module based Intel Celeron processor with on-die L2 cache will not be expecting to see a

Maximum CPUID Input Value greater than 2, it is not possible to predict how software will behave on

processors with this erratum. Software using the fact that bit 18 in the feature flags is set, to determine the

presence of the Pentium

III processor serial number feature, without also verifying that it is executing on a

Pentium III processor, may incorrectly believe that the Mobile Module based Intel Celeron processor with on-die

L2 cache, support the processor serial number feature. However, the values the CPUID instruction returns

when CPUID is executed with EAX=3 will not be the processor serial number and will be undefined.

Workaround: It is possible for BIOS code to contain a workaround for this erratum.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.