Specification Update

MOBILE INTEL

CELERON

PROCESSOR at 466 MHz, 433 MHz, 400 MHz,

366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE

H46. Machine Check Exception May Occur Due to Improper Line

Eviction in the IFU

Problem: The Mobile Intel Celeron processor is designed to signal an unrecoverable Machine Check

Exception (MCE) as a consistency checking mechanism. Under a complex set of circumstances involving

multiple speculative branches and memory accesses there exists a one cycle long window in which the

processor may signal a MCE in the Instruction Fetch Unit (IFU) because instructions previously decoded have

been evicted from the IFU. The one cycle long window is opened when an opportunistic fetch receives a partial

hit on a previously executed but not as yet completed store resident in the store buffer. The resulting partial hit

erroneously causes the eviction of a line from the IFU at a time when the processor is expecting the line to still

be present. If the MCE for this particular IFU event is disabled, execution will continue normally.

Implication: While this erratum may occur on a system with any number of processors, the probability of

occurrence increases with the number of processors. If this erratum does occur, a machine check exception will

result. Note systems that implement an operating system that does not enable the Machine Check Architecture

will be completely unaffected by this erratum, e.g., Windows* 95 and Windows 98.

Workaround: It is possible for BIOS code to contain a workaround for this erratum.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

H47 Lower Bits of SMRAM SMBASE Register Cannot Be Written

With an ITP

Problem: The System Management Base (SMBASE) register (7EF8H) stores the starting address of the

System Management RAM (SMRAM). This register is used by the processor when it is in System Management

Mode (SMM), and its contents serve as the memory base for code execution and data storage. The 32-bit

SMBASE register can normally be programmed to any value. When programmed with an In-Target Probe (ITP),

however, any attempt to set the lower 11 bits of SMBASE to anything other than zeros via the WRMSR

instruction will cause the attempted write to fail.

Implication: When set via the ITP, any attempt to relocate SMRAM space must be made with 2 Kbyte

alignment.

Workaround: None identified

Status: For the steppings affected see the Summary of Changes at the beginning of this section.