Specification Update

MOBILE INTEL

CELERON

PROCESSOR at 466 MHz, 433 MHz, 400 MHz,

366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE

H48.

Task Switch May Cause Wrong PTE and PDE Access Bit

to be Set

Problem: If an operating system executes a task switch via a Task State Segment (TSS), and the TSS is

wholly or partially located within a clean page (A and D bits clear) and the GDT entry for the new TSS is either

misaligned across a cache line boundary or is in a clean page, the accessed and dirty bits for an incorrect page

table/directory entry may be set.

Implication: An operating system that uses hardware task switching (or hardware task management) may

encounter this erratum. The effect of the erratum depends on the alignment of the TSS and ranges from no

anomalous behavior to unexpected errors.

Workaround: The operating system could align all TSSs to be within page boundaries and set the A and D

bits for those pages to avoid this erratum. The operating system may alternately use software task

management.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

H49. Unsynchronized Cross-Modifying Code Operations Can

Cause Unexpected Instruction Execution Results

Problem: The act of one processor, or system bus master, writing data into a currently executing code

segment of a second processor with the intent of having the second processor execute that data as code is

called cross-modifying code (XMC). XMC that does not force the second processor to execute a synchronizing

instruction, prior to execution of the new code, is called unsynchronized XMC.

Software using unsynchronized XMC to modify the instruction byte stream of a processor can see unexpected

instruction execution from the processor which is executing the modified code.

Implication: In this case, the phrase "unexpected execution behavior" encompasses the generation of most

of the exceptions listed in the Intel Architecture Software Developer's Manual Volume 3: System Programming

Guide including a General Protection Fault (GPF). In the event of a GPF, the application executing the

unsynchronized XMC operation would be terminated by the operating system.

Workaround: In order to avoid this erratum, programmers should use the XMC synchronization algorithm as

detailed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide, Section

7.1.3.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.