Specification Update

MOBILE INTEL

CELERON

PROCESSOR at 466 MHz, 433 MHz, 400 MHz,

366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE

H52.

Floating-Point Exception Condition May Be Deferred

Problem: A floating-point instruction that causes a pending floating-point exception (ES=1) is

normally signaled by the processor on the next waiting FP/MMX™ technology instruction. In the

following set of circumstances, the exception may be delayed or the FSW register may contain a

wrong value:

1. The excepting floating-point instruction is followed by an instruction that accesses memory across a

page (4-Kbyte) boundary or its access results in the update of a page table dirty/access bit.

2. The memory accessing instruction is immediately followed by a waiting floating-point or MMX

technology instruction.

3. The waiting floating-point or MMX technology instruction retires during a one-cycle window that

coincides with a sequence of internal events related to instruction cache line eviction.

Implication: The floating-point exception will not be signaled until the next waiting floating-

point/MMX technology instruction. Alternatively, it may be signaled with the wrong TOS and

condition code values. This erratum has not been observed in any commercial software

applications.

Workaround: None identified

Status: For the stepping affected see the Summary of Changes at the beginning of this section.