Specification Update

MOBILE INTEL

CELERON

PROCESSOR at 466 MHz, 433 MHz, 400 MHz,

366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE

H53. Race Conditions May Exist on Thermal Sensor SMBus

Collision Detection/Arbitration Circuitry

Problem: In certain SMBus configurations, when the thermal sensor is used in “hard wired alert” mode along

with at least one other device on the bus, the thermal sensor may continue to send its address after losing a

collision arbitration in response to an Alert Response Address (ARA) by the SMBus controller.

In order for this erratum to occur, all of the following conditions must be present:

1. The thermal sensor must be configured with alert enabled (default setting).

2. There must be one or more other devices on the SMBus along with the thermal sensor.

3. One or more of these other devices must be also configured with the alert enabled.

4. One or more of these other devices must have a lower address (higher priority) than the thermal sensor.

5. The thermal sensor must generate an SM alert while at least one other device has an SM alert pending to

be serviced.

In this situation, the thermal sensor will continue to send its address on the SMBus even if it has a lower priority

than the pending alert. When this occurs, the SMBus controller cannot correctly interpret the device address.

This may cause the thermal sensor’s alert flag not to clear and may result in SMBus lockup.

Implication: The SMBus controller may see an invalid address and the resulting response of the SMBus

controller will vary from implementation to implementation.

Workaround: Remove any one of the five conditions listed above or:

1. In software, use polling mode for the thermal sensor data collection with alert disabled. This software

workaround has been validated on both Intel’s test platforms as well as on certain OEM systems.

2. Ensure that the thermal sensor alert may be cleared by a hardware or software mechanism. The

implementation of this workaround will be system dependent.

Status: For the steppings affected, see the Summary of Changes at the beginning of this section.

H54. Intermittent Power-on Failure Due To Uninitialized Processor

Internal Nodes

Problem: If there is no clock source supplied to the processor’s PICCLK pin, the processor may drive an

incorrect address for the reset vector at power-on due to uninitialized processor internal nodes. In this scenario

when ADS# is asserted, it is possible that the processor drives either the SMI or NMI vector addresses, rather

than the reset vector address.

Implication: Systems that provide a clock to the processor’s PICCLK pin are unaffected by this issue. On a

system implementation with no clock source supplied to the processor’s PICCLK pin, a small percentage of the

systems may intermittently fail to boot, or may fail to resume from a STR or STD state. On the next power-on,

the system will likely boot normally.

Workaround: Supply a clock source to the processor’s PICCLK pin.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.