Specification Update

MOBILE INTEL
®
CELERON
®
PROCESSOR at 466 MHz, 433 MHz, 400 MHz,
366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE
47
H64.
Processor Incorrectly Samples NMI Interrupt after RESET#
Deassertion When Processor APIC is Hardware-Disabled
Problem: When the processor APIC is hardware-disabled the processor may incorrectly interpret the NMI
signal as an NMI interrupt, instead of a frequency strap value, starting six bus clocks after RESET# is de-
asserted. This will result in a processor hang due to the NMI Handler not being installed at this time.
Implication: The system may fail to boot due to this issue.
Workaround: The processor APIC must be hardware-enabled by pulling PICD[1:0] high with separate pull up
resistors and supplying PICCLK to the processor.
Status: For the steppings affected, see the Summary of Changes at the beginning of this section.
H65.
The Instruction Fetch Unit (IFU) May Fetch Instructions
Based Upon Stale CR3 Data After a Write to CR3 Register
Problem - Under a complex set of conditions, there exists a one clock window following a write to the CR3
register where-in it is possible for the iTLB fill buffer to obtain a stale page translation based on the stale CR3
data. This stale translation will persist until the next write to the CR3 register, the next page fault or execution of
a certain class of instructions including RDTSC, CPUID, or IRETD with privilege level change.
Implication - The wrong page translation could be used leading to erroneous software behavior.
Workaround - Operating systems that are potentially affected can add a second write to the CR3 register.
Status - For the steppings affected, see the Summary of Changes at the beginning of this section.