Intel Celeron D Processor 3xx Sequence

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Pin Listing and Signal Descriptions

Datasheet 43

D26# H24 Source Synch Input/Output

D27# M21 Source Synch Input/Output

D28# L22 Source Synch Input/Output

D29# J24 Source Synch Input/Output

D30# K23 Source Synch Input/Output

D31# H25 Source Synch Input/Output

D32# M23 Source Synch Input/Output

D33# N22 Source Synch Input/Output

D34# P21 Source Synch Input/Output

D35# M24 Source Synch Input/Output

D36# N23 Source Synch Input/Output

D37# M26 Source Synch Input/Output

D38# N26 Source Synch Input/Output

D39# N25 Source Synch Input/Output

D40# R21 Source Synch Input/Output

D41# P24 Source Synch Input/Output

D42# R25 Source Synch Input/Output

D43# R24 Source Synch Input/Output

D44# T26 Source Synch Input/Output

D45# T25 Source Synch Input/Output

D46# T22 Source Synch Input/Output

D47# T23 Source Synch Input/Output

D48# U26 Source Synch Input/Output

D49# U24 Source Synch Input/Output

D50# U23 Source Synch Input/Output

D51# V25 Source Synch Input/Output

D52# U21 Source Synch Input/Output

D53# V22 Source Synch Input/Output

D54# V24 Source Synch Input/Output

D55# W26 Source Synch Input/Output

D56# Y26 Source Synch Input/Output

D57# W25 Source Synch Input/Output

D58# Y23 Source Synch Input/Output

D59# Y24 Source Synch Input/Output

D60# Y21 Source Synch Input/Output

D61# AA25 Source Synch Input/Output

D62# AA22 Source Synch Input/Output

D63# AA24 Source Synch Input/Output

DBI0# E21 Source Synch Input/Output

DBI1# G25 Source Synch Input/Output

DBI2# P26 Source Synch Input/Output

Table 4-1. Alphabetical Pin Assignment

Pin Name Pin #

Signal Buffer

Type

Direction

DBI3# V21 Source Synch Input/Output

DBR# AE25 Power/Other Output

DBSY# H5 Common Clock Input/Output

DEFER# E2 Common Clock Input

DP0# J26 Common Clock Input/Output

DP1# K25 Common Clock Input/Output

DP2# K26 Common Clock Input/Output

DP3# L25 Common Clock Input/Output

DRDY# H2 Common Clock Input/Output

DSTBN0# E22 Source Synch Input/Output

DSTBN1# K22 Source Synch Input/Output

DSTBN2# R22 Source Synch Input/Output

DSTBN3# W22 Source Synch Input/Output

DSTBP0# F21 Source Synch Input/Output

DSTBP1# J23 Source Synch Input/Output

DSTBP2# P23 Source Synch Input/Output

DSTBP3# W23 Source Synch Input/Output

FERR#/PBE# B6 Asynch AGL+ Output

GTLREF AA21 Power/Other Input

GTLREF AA6 Power/Other Input

GTLREF F20 Power/Other Input

GTLREF F6 Power/Other Input

HIT# F3 Common Clock Input/Output

HITM# E3 Common Clock Input/Output

IERR# AC3 Asynch GTL+ Output

IGNNE# B2 Asynch GTL+ Input

INIT# W5 Asynch GTL+ Input

ITP_CLK0 AC26 TAP Input

ITP_CLK1 AD26 TAP Input

LINT0 D1 Asynch GTL+ Input

LINT1 E5 Asynch GTL+ Input

LOCK# G4 Common Clock Input/Output

MCERR# V6 Common Clock Input/Output

OPTIMIZED/

COMPAT#

AE26 Power/Other Input

PROCHOT# C3 Asynch GTL+ Input/Output

PWRGOOD AB23 Power/Other Input

REQ0# J1 Source Synch Input/Output

REQ1# K5 Source Synch Input/Output

REQ2# J4 Source Synch Input/Output

REQ3# J3 Source Synch Input/Output

REQ4# H3 Source Synch Input/Output

Table 4-1. Alphabetical Pin Assignment

Pin Name Pin #

Signal Buffer

Type

Direction