Specification Update

Errata
Specification Update 55
W51. The Processor May Report a #TS Instead of a #GP Fault
Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid
TSS exception) instead of a #GP fault (general protection exception).
Implication: Operation systems that access a busy TSS may get invalid TSS fault
instead of a #GP fault. Intel has not observed this erratum with any
commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W52. BTS Message May Be Lost When the STPCLK# Signal Is
Active
Problem: STPCLK# is asserted to enable the processor to enter a low-power
state. Under some circumstances, when STPCLK# becomes active, a
pending BTS (Branch Trace Store) message may be either lost and not
written or written with corrupted branch address to the Debug Store
area.
Implication: BTS messages may be lost in the presence of STPCLK# assertions.
Workaround: None identified.
Status: For affected steppings see the Summary Tables of Changes.
W53. Last Exception Record (LER) MSRs May Be Incorrectly
Updated
Problem: The LASTINTTOIP and LASTINTFROMIP MSRs (1DDH-1DEH) may
contain incorrect values after the following events: masked SSE2
floating-point exception, StopClk, NMI and INT.
Implication: The value of the LER MSR may be incorrectly updated to point to a
SIMD Floating-Point instruction even though no exception occurred on
that instruction or to point to an instruction that was preceded by a
StopClk interrupt or rarely not to be updated on Interrupts (NMI and
INT).
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.