Specification Update

Errata
56 Specification Update
W54. Writing the Local Vector Table (LVT) When an Interrupt Is
Pending May Cause an Unexpected Interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an
interrupt may be taken on the new interrupt vector even if the mask bit
is set.
Implication: An interrupt may immediately be generated with the new vector when
an LVT entry is written, even if the new LVT entry has the mask bit set.
If there is no Interrupt Service Routine (ISR) set up for that vector the
system will GP fault. If the ISR does not do an End of Interrupt
(EOI) the bit for the vector will be left set in the in-service register and
mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if
that vector was programmed as masked. This ISR routine must do an EOI to clear any
unexpected interrupts that may occur. The ISR associated with the spurious vector
does not generate an EOI; therefore the spurious vector should not be used when
writing the LVT.
Status: For the steppings affected, see the Summary Tables of Changes.
W55. Removed – See Erratum W3
W56. FP Inexact-Result Exception Flag May Not Be Set
Problem: When the result of a floating-point operation is not exactly represented in
the destination format (1/3 in binary form, for example), an inexact-
result (precision) exception occurs. When this occurs, the PE bit (bit 5
of the FPU status word) is normally set by the processor. Under certain
rare conditions, this bit may not be set when this rounding occurs.
However, other actions taken by the processor (invoking the software
exception handler if the exception is unmasked) are not affected. This
erratum can only occur if the floating-point operation which causes the
precision exception is immediately followed by one of the following
instructions:
FST m32real
FST m64real
FSTP m32real
FSTP m64real
FSTP m80real
FIST m16int
FIST m32int
FISTP m16int
FISTP m32int
FISTP m64int