Specification Update

Errata
72 Specification Update
W95. Microcode Updates Performed During VMX Non-root
Operation Could Result in Unexpected Behavior
Problem: When Intel® Virtualization Technology is enabled, microcode updates
are allowed only during VMX root operations. Attempts to apply
microcode updates while in VMX non-root operation should be silently
ignored. Due to this erratum, the processor may allow microcode
updates during VMX non-root operations if not explicitly prevented by
the host software.
Implication: Microcode updates performed in non-root operation may result in
unexpected system behavior.
Workaround: Host software should intercept and prevent loads to IA32_BIOS_UPDT_TRIG MSR
(79H) during VMX non-root operations. There are two mechanism that can be used (1)
Enabling MSR access protection in the VM-execution controls or (2) Enabling selective
MSR protection of IA32_BIOS_UPDT_TRIG MSR.
Status: For affected steppings see the Summary Table of Changes.
W96. Single Step Interrupts with Floating Point Exception
Pending May Be Mishandled
Problem: In certain circumstances, when a floating point exception (#MF) is pending
during single-step execution, processing of the single-step debug
exception (#DB) may be mishandled.
Implication: When this erratum occurs, #DB will be incorrectly handled as follows:
• #DB is signaled before the pending higher priority #MF (Interrupt 16)
• #DB is generated twice on the same instruction
Workaround: None Identified
Status: For the steppings affected, see the Summary Tables of Changes.