Specification Update

Errata
76 Specification Update
Status: For the steppings affected, see the Summary Tables of Changes.
W106. (E)CX May Get Incorrectly Updated When Performing Fast
String REP MOVS or Fast String REP STOS with Large Data
Structures
Problem: When performing Fast String REP MOVS or REP STOS commands with data
structures [(E)CX*Data Size] larger than the supported address size
structure (64K for 16-bit address size and 4G for 32-bit address size)
some addresses may be processed more than once. After an amount of
data greater than or equal to the address size structure has been
processed, external events (such as interrupts) will cause the (E)CX
registers to be increment by a value that corresponds to 64K bytes for
16 bit address size and 4G bytes for 32 bit address size.
Implication: (E)CX may contain an incorrect count which may cause some of the
MOVS or STOS operations to re-execute. Intel has not observed this
erratum with any commercially available software.
Workaround: Do not use values in (E)CX that when multiplied by the data size give values larger
than the address space size (64 kB for 16-bit address size and 4 GB for
32-bit address size).
Status: For the steppings affected, see the Summary Tables of Changes.
W107. Upper 32 bits of 'From' Address Reported through BTMs or
BTSs May Be Incorrect
Problem: When a far transfer switches the processor from 32-bit mode to IA-32e
mode, the upper 32 bits of the 'From' (source) addresses reported
through the BTMs (Branch Trace Messages) or BTSs (Branch Trace
Stores) may be incorrect.
Implication: The upper 32 bits of the 'From' address debug information reported
through BTMs or BTSs may be incorrect during this transition.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.