Specification Update

Errata
78 Specification Update
W110. REP CMPS/SCAS Operations May Terminate Early in 64-bit
Mode when RCX >= 0X100000000
Problem: REP CMPS (Compare String) and SCAS (Scan String) instructions in 64-bit
mode may terminate before the count in RCX reaches zero if the initial
value of RCX is greater than or equal to 0X100000000.
Implication: Early termination of REP CMPS/SCAS operation may be observed and
RFLAGS may be incorrectly updated.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
W111. FXSAVE/FXRSTOR Instructions which Store to the End of
the Segment and Cause a Wrap to a Misaligned Base
Address (Alignment <= 0x10h) May Cause FPU
Instruction or Operand Pointer Corruption
Problem: If a FXSAVE/FXRSTOR instruction stores to the end of the segment
causing a wrap to a misaligned base address (alignment <= 0x10h),
and one of the following conditions is satisfied:
1. 32-bit addressing, obtained by using address-size override, when in 64-bit mode.
2. 16-bit addressing in legacy or compatibility mode.
Then, depending on the wrap-around point, one of the below saved values may be
corrupted:
• FPU Instruction Pointer Offset
• FPU Instruction Pointer Selector
• FPU Operand Pointer Selector
• FPU Operand Pointer Offset
Implication: This erratum could cause FPU instruction or operand pointer corruption
and may lead to unexpected operations in the floating point exception
handler.
Workaround: Avoid segment base misalignment and address wrap-around at the segment boundary.
Status: For the steppings affected, see the Summary Tables of Changes.