Specification Update

Errata
Specification Update 79
W112. PREFETCHh Instruction Execution under Some Conditions
May Lead to Processor Livelock
Problem: PREFETCHh instruction execution after a split load and dependent upon
ongoing store operations may lead to processor livelock.
Implication: Due to this erratum, the processor may livelock.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
W113. PREFETCHh Instructions May Not Be Executed When
Alignment Check (AC) is Enabled
Problem: PREFETCHT0, PREFETCHT1, PREFETCHT2 and PREFETCHNTA instructions
may not be executed when alignment check is enabled.
Implication: PREFETCHh instructions may not perform the data prefetch if Alignment
Check is enabled.
Workaround: Clear the AC flag (bit 18) in the EFLAGS register and/or the AM bit (bit 18) of Control
Register CR0 to disable alignment checking.
Status: For the steppings affected, see the Summary Tables of Changes.
W114. Upper 32 Bits of the FPU Data (Operand) Pointer in the
FXSAVE Memory Image May Be Unexpectedly All 1's after
FXSAVE
Problem: The upper 32 bits of the FPU Data (Operand) Pointer may incorrectly be
set to all 1's instead of the expected value of all 0's in the FXSAVE
memory image if all of the following conditions are true:
• The processor is in 64-bit mode.
• The last floating point operation was in compatibility mode
• Bit 31 of the FPU Data (Operand) Pointer is set.
• An FXSAVE instruction is executed
Implication: Software depending on the full FPU Data (Operand) Pointer may behave
unpredictably.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.