Specification Update

Errata
80 Specification Update
W115. Performance Monitor IDLE_DURING_DIV (18h) Count May
Not Be Accurate
Problem: Performance monitoring events that count the number of cycles the
divider is busy and no other execution unit operation or load operation
is in progress may not be accurate.
Implication: The counter may reflect a value higher or lower than the actual number
of events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W116. SYSCALL Immediately after Changing EFLAGS.TF May Not
Behave According to the New EFLAGS.TF
Problem: If a SYSCALL instruction follows immediately after EFLAGS.TF was updated
and IA32_FMASK.TF (bit 8) is cleared, then under certain
circumstances SYSCALL may behave according to the previous
EFLAGS.TF.
Implication: When the problem occurs, SYSCALL may generate an unexpected
debug exception, or may skip an expected debug exception.
Workaround: Mask EFLAGS.TF by setting IA32_FMASK.TF (bit 8).
Status: For the steppings affected, see the Summary Tables of Changes.
W117. IA32_FMASK Is Reset during an INIT
Problem: IA32_FMASK MSR (0xC0000084) is reset during INIT.
Implication: If an INIT takes place after IA32_FMASK is programmed, the processor
will overwrite the value back to the default value.
Workaround: Operating system software should initialize IA32_FMASK after INIT.
Status: For the steppings affected, see the Summary Tables of Changes.