Specification Update

Errata
Specification Update 81
W118. IO_SMI Indication in SMRAM State Save Area May Be Set
Incorrectly
Problem: The IO_SMI bit in SMRAM's location 7FA4H is set to "1" by the CPU to
indicate a System Management Interrupt (SMI) occurred as the result
of executing an instruction that reads from an I/O port. Due to this
erratum, the IO_SMI bit may be incorrectly set by:
• A non-I/O instruction.
• SMI is pending while a lower priority event interrupts.
• A REP I/O read.
• An I/O read that redirects to MWAIT.
Implication: SMM handlers may get false IO_SMI indication.
Workaround: The SMM handler has to evaluate the saved context to determine if the SMI was
triggered by an instruction that read from an I/O port. The SMM
handler must not restart an I/O instruction if the platform has not been
configured to generate a synchronous SMI for the recorded I/O port
address.
Status: For the steppings affected, see the Summary Tables of Changes.
W119. LBR, BTS, BTM May Report a Wrong Address When an
Exception/Interrupt Occurs in 64-bit Mode
Problem: An exception/interrupt event should be transparent to the LBR (Last
Branch Record), BTS (Branch Trace Store) and BTM (Branch Trace
Message) mechanisms. However, during a specific boundary condition
where the exception/interrupt occurs right after the execution of an
instruction at the lower canonical boundary (0x00007FFFFFFFFFFF) in
64-bit mode, the LBR return registers will save a wrong return address
with bits 63 to 48 incorrectly sign extended to all 1’s. Subsequent BTS
and BTM operations which report the LBR will also be incorrect.
Implication: LBR, BTS and BTM may report incorrect information in the event of an
exception/interrupt.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.