Specification Update

Errata
86 Specification Update
W131. Performance Monitor SSE Retired Instructions May Return
Incorrect Values
Problem: The SIMD_INST_RETIRED (Event: C7H) is used to track retired SSE
instructions. Due to this erratum, the processor may inaccurately count
certain types of instructions resulting in values higher than the number
of actual retired SSE instructions.
Implication: The event monitor instruction SIMD_INST_RETIRED may report count
higher than expected.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W132. Performance Monitoring Events for L1 and L2 Miss May
Not Be Accurate
Problem: Performance monitoring events 0CBh with an event mask value of 02h or
08h (MEM_LOAD_RETIRED.L1_LINE_MISS or
MEM_LOAD_RETIRED.L2_LINE_MISS) may under count the cache miss
events.
Implication: These performance monitoring events may show a count which is lower
than expected; the amount by which the count is lower is dependent on
other conditions occurring on the same load that missed the cache.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W133. A MOV Instruction from CR8 Register with 16 Bit Operand
Size Will Leave Bits 63:16 of the Destination Register
Unmodified
Problem: Moves to/from control registers are supposed to ignore REW.W and the
66H (operand size) prefix. In systems supporting Intel Virtualization
Technology, when the processor is operating in VMX non-root operation
and “use TPR shadow” VM-execution control is set to 1, a MOV
instruction from CR8 with a 16 bit operand size (REX.W =0 and 66H
prefix) will only store 16 bits and leave bits 63:16 at the destination
register unmodified, instead of storing zeros in them.
Implication: Intel has not observed this erratum with any commercially available
software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.