Specification Update

Errata
Specification Update 87
W134. Debug Register May Contain Incorrect Information on a
MOVSS or POPSS Instruction followed by SYSRET
Problem: In IA-32e mode, if a MOVSS or POPSS instruction with a debug breakpoint
is followed by the SYSRET instruction; incorrect information may exist
in the Debug Status Register (DR6).
Implication: When debugging or when developing debuggers, this behavior should
be noted. This erratum does not occur under normal usage of the
MOVSS or POPSS instructions (that is, following them with a MOV ESP
instruction).
Workaround: Do not attempt to put a breakpoint on MOVSS and POPSS instructions that are
followed by a SYSRET.
Status: For the steppings affected, see the Summary Tables of Changes.
W135. Update of Read/Write (R/W) or User/Supervisor (U/S) or
Present (P) Bits without TLB Shootdown May Cause
Unexpected Processor Behavior
Problem: Updating a page table entry by changing R/W, U/S or P bits without TLB
shootdown (as defined by the 4 step procedure in "Propagation of Page
Table and Page Directory Entry Changes to Multiple Processors" In
volume 3A of the Intel® 64 and IA-32 Architecture Software
Developer’s Manual), in conjunction with a complex sequence of
internal processor micro-architectural events, may lead to unexpected
processor behavior.
Implication: This erratum may lead to livelock, shutdown or other unexpected
processor behavior. Intel has not observed this erratum with any
commercially available system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W136. Update of Attribute Bits on Page Directories without
Immediate TLB Shootdown May Cause Unexpected
Processor Behavior
Problem: Updating a page directory entry (or page map level 4 table entry or page
directory pointer table entry in IA-32e mode) by changing R/W, U/S or
P bits without immediate TLB shootdown (as described by the 4 step
procedure in "Propagation of Page Table and Page Directory Entry
Changes to Multiple Processors" In Volume 3A of the Intel® 64 and IA-
32 Architecture Software Developer’s Manual), in conjunction with a
complex sequence of internal processor micro-architectural events, may
lead to unexpected processor behavior.
Implication: This erratum may lead to livelock, shutdown or other unexpected
processor behavior. Intel has not observed this erratum with any
commercially available system.