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Datasheet 11
Low Power Features
2 Low Power Features
2.1 Clock Control and Low Power States
The processor supports the C1/AutoHALT, C1/MWAIT, C2, and C3 core low-power
states, along with their corresponding package-level states for power management.
These package states include Normal, Stop Grant, Stop Grant Snoop, Sleep, and Deep
Sleep. The processor’s central power management logic enters a package low-power
state by initiating a P_LVLx (P_LVL2, P_LVL3) I/O read to the Intel 965 Express Chipset
family. Figure 1 shows the package-level low-power states and Figure 2 shows the core
low-power states. Refer to Table 1 for a mapping of core low-power states to package
low-power states.
The processor implements two software interfaces for requesting low-power states:
MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK
register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are
converted to equivalent MWAIT C-state requests inside the processor and do not
directly result in I/O reads on the processor FSB. The monitor address does not need to
be setup before using the P_LVLx I/O read interface. The sub-state hints used for each
P_LVLx read can be configured through the IA32_MISC_ENABLES Model Specific
Register (MSR).
If the processor encounters a chipset break event while STPCLK# is asserted, it asserts
the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to
system logic that the processor should return to the Normal state.
NOTE: AutoHALT or MWAIT/C1
Table 1. Coordination of Core-Level Low-Power States at the Package Level
Core States Package States
C0 Normal
C1
(1)
Normal
C2 Stop Grant
C3 Deep Sleep
Figure 1. Package-Level Low-Power States
Stop
Grant
Snoop
Normal
Stop
Grant
Deep
Sleep
STPCLK# asserted
Snoop
serviced
Snoop
occurs
Sleep
SLP# asserted
SLP# de-asserted
DPSLP# asserted
DPSLP# de-asserted
STPCLK# de-asserted