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Package Mechanical Specifications and Pin Information
60 Datasheet
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TRDY# Input
TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both FSB agents.
TRST# Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
V
CC
Input Processor core power supply.
V
CCA
Input V
CCA
provides isolated power for the internal processor core PLL’s.
V
CCP
Input Processor I/O Power Supply.
V
CC_SENSE
Output
V
CC_SENSE
together with V
SS_SENSE
are voltage feedback signals to
Intel® MVP 6 that control the 2.1-mΩ loadline at the processor die.
It should be used to sense or measure power near the silicon with
little noise.
VID[6:0] Output
VID[6:0] (Voltage ID) pins are used to support automatic selection of
power supply voltages (V
CC
). Unlike some previous generations of
processors, these are CMOS signals that are driven by the processor.
The voltage supply for these pins must be valid before the VR can
supply V
CC
to the processor. Conversely, the VR output must be
disabled until the voltage supply for the VID pins becomes valid. The
VID pins are needed to support the processor voltage specification
variations. See Table 2 for definitions of these pins. The VR must
supply the voltage that is requested by the pins, or disable itself.
V
SS_SENSE
Output
V
SS_SENSE
together with V
CC_SENSE
are voltage feedback signals to
Intel MVP 6 that control the 2.1-mΩ loadline at the processor die. It
should be used to sense or measure ground near the silicon with little
noise.
Table 15. Signal Description (Sheet 8 of 8)
Name Type Description