Intel Celeron Processor Specification Update

INTEL
®
CELERON® PROCESSOR SPECIFICATION UPDATE
92
The Intel Architecture Software Developer's Manual, Vol 3: System Programming Guide
Section
15.9.6 " Programming the Performance Counters for Non-Retirement Events" page 15 - 37, Figure
15-12, first row currently states:
63 0
It should state:
31 0
The
Intel Architecture Software Developer's Manual, Vol 1: Basic Architecture Chapter 12, section 12.5.2 on
Figure 12-2 (I/O Permission Bit Map) currently states:
Last byte of bit map must be followed by a byte with all bits.
It should state:
Last byte of bit map must be followed by a byte with all bits set.
Also, in the lower left hand Conner of Figure 12-2 (I/O Permission Bit Map) currently states:
Last I/O base map must be
It should state:
Last I/O base map must be less than or equal to DFFFH
C20. Figure 15-12 PEBS Record Format
EFLAGS
EFLAGS
C21.
I/O Permission Bit Map