Intel Celeron Processor Specification Update

INTEL
®
CELERON® PROCESSOR SPECIFICATION UPDATE
14
Summary of Errata
NO. CPUID/Stepping Plans ERRATA
650h
A0
651h
A1
660h
A0
665h
B0
683h
B0
686h
C0
68Ah
D0
6B1h
A1
6B4h
B1
C26 X X X X Fixed Test pin must be high during
power up
C27 X X X X X X X X Fixed Intervening writeback may
occur during locked
transaction
C28 X X X X X X X X X NoFix MC2_STATUS MSR has
model-specific error code
and machine check
architecture error code
reversed
C29 X X X X X X X X X NoFix MOV with debug register
causes debug exception
C30 X X X X X X X X X NoFix Upper four PAT entries not
usable with Mode B or Mode
C paging
C31 X X Fixed Incorrect memory type may
be used when MTRRs are
disabled
C32 X X X Fixed Misprediction in program
flow may cause unexpected
instruction execution
C33 X X X X X X X X X NoFix Data Breakpoint Exception in
a displacement relative near
call may corrupt EIP
C34 X X X X X X X X X NoFix System bus ECC not
functional with 2:1 ratio
C35 X X X X X X X Fixed Fault on REP CMPS/SCAS
operation may cause
incorrect EIP
C36 X X X X X X X NoFix RDMSR and WRMSR to
invalid MSR address may not
cause GP fault
C37 X X X X X X X NoFix SYSENTER/SYSEXIT
instructions can implicitly
load “null segment selector”
to SS and CS registers
C38 X X X X X X X NoFix PRELOAD followed by
EXTEST does not load
boundary scan data
C39 X X X X X X Fixed Far jump to new TSS with D-
bit cleared may cause
system hang