Intel Celeron Processor Specification Update

INTEL
®
CELERON® PROCESSOR SPECIFICATION UPDATE
17
Summary of Errata
NO. CPUID/Stepping Plans ERRATA
650h
A0
651h
A1
660h
A0
665h
B0
683h
B0
686h
C0
68Ah
D0
6B1h
A1
6B4h
B1
C68 X NoFix Snoop probe during FLUSH#
could cause L2 to be left in
shared state
C69 X Fixed Livelock May Occur Due to
IFU Line Eviction
C70 X X X X X Fixed Selector for the LTR/LLDT
register may get corrupted
C71 X X X X X X X X X NoFix
INIT does not clear global
entries in the TLB
C72 X X X X X X X X X NoFix
VM bit will be cleared on a
double fault handler
C73 X X X X X X X X X NoFix
Memory aliasing with
inconsistent A and D bits
may cause processor
deadlock
C74 X X X X X X X X X
NoFix
Processor may report invalid
TSS fault instead of Double
fault during mode C paging
C75 X X Fixed APIC failure at CPU
core/system bus frequency
of 766/66 MHz
C76 X X X X X X X X X NoFix Machine check exception
may occur when interleaving
code between different
memory types
C77 X X X X X X X X X NoFix Wrong ESP Register Values
During a Fault in VM86 Mode
C78 X X X X X X X X X NoFix APIC ICR Write May Cause
Interrupt Not to be Sent
When ICR Delivery Bit
Pending
C79 X X X X X X X X Fixed The instruction fetch unit
(IFU) may fetch
instructions based upon stale
CR3 data after a write to
CR3 Register
C80 X NoFix Processor Might not Exit
Sleep State Properly Upon
De-assertion of CPUSLP#
Signal
C81 X X NoFix During Boundary Scan, BCLK
not Sampled High When