Intel Celeron Processor Specification Update

INTEL

CELERON® PROCESSOR SPECIFICATION UPDATE

C87. The FXSAVE, STOS, or MOVS Instructions May Cause a Store

Ordering Violation When Data Crosses a Page with a UC

Memory Type

Problem: If the data from an FXSAVE, STOS, or MOVS instruction crosses a page

boundary from WB to UC memory type and this instruction is immediately

followed by a second instruction that also issues a store to memory, the final data

stores from both instructions may occur in the wrong order.

Implication: The impact of this store ordering behavior may vary from normal software

execution to potential software failure. Intel has not observed this erratum in

commercially available software.

Workaround: FXSAVE, STOS, or MOVS data must not cross page boundary from WB to UC

memory type.

Status: For the steppings affected, see the Summary Tables of Changes.

C88. POPF and POPFD Instructions that Set the Trap Flag Bit May

Cause Unpredictable Processor Behavior

Problem: In some rare cases, POPF and POPFD instructions that set the Trap Flag (TF) bit in the

EFLAGS register (causing the processor to enter Single-Step mode) may cause

unpredictable processor behavior.

Implication: Single step operation is typically enabled during software debug activities, not during

normal system operation.

Workaround: There is no workaround for single step operation in commercially available software. For

debug activities on custom software, the POPF and POPFD instructions could be

immediately followed by a NOP instruction to facilitate correct execution

Status: For the steppings affected, see the Summary Tables of Changes

C89. Code Segment Limit Violation May Occur on 4 Gigabyte Limit

Check

Problem: Code Segment limit violation may occur on 4 Gigabyte limit check when the

code stream wraps around in a way that one instruction ends at the last byte of

the segment and the next instruction begins at 0x0.