Intel Celeron Processor Specification Update

INTEL
®
CELERON® PROCESSOR SPECIFICATION UPDATE
83
The
Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Appendix A, Table A-2,
the opcode corresponding to 0x33 currently states:
Gb, Ev
It should state:
Gv, Ev
Also, Page 3-791, XOR-Logical Exclusive OR, the two entries for opcode 33 currently state:
Opcode Instruction Description
33 /r XOR r16,r/m16 r8 XOR r/m8
33 /r XOR r32,r/m32 r8 XOR r/m8
It should state:
Opcode Instruction Description
33 /r r16 XOR r/m16 r8 XOR r/m8
33 /r r32 XOR r/m32 r8 XOR r/m8
C10. Incorrect Information for SLDT
In the
Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference, the
opcode/Instruction/Description table for SLDT currently states “SLDT
r/m32 Store segment selector from
LDTR in low-order 16 bits of
r/m32” but should instead list “SLDT r32 Store segment selector from LDTR in
low-order 16 bits of
r32.”
In the
Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference, the sentence in the
LGDT/LIDT instruction section currently states:
”See 'SFENCE -- Store Fence' in this chapter for information on storing the contents of the GDTR
and IDTR."
It should state:
"See 'SGDT/SIDT' in this chapter for information on storing the contents of the GDTR and IDTR."
C9. 0x33 Opcode
C11. LGDT/LIDT Instruction Information Correction