Uncore Manual

Reference Number: 329468-002 99
Uncore Performance Monitoring
IRP Performance Monitoring
2.6 IRP PERFORMANCE MONITORING
2.6.1 Overview of the R2PCIe Box
IRP is responsible for maintaining coherency for IIO traffic that needs to be coherent (e.g. cross-
socket P2P).
2.6.2 IRP Performance Monitoring Overview
The IRP Box supports event monitoring through two sets of two 48b wide counters
(IRP{0,1}_PCI_PMON_CTR/CTL{1:0}). Each of these four counters can be programmed to count any
IRP event. The IRP counters can increment by a maximum of 8b per cycle.
For information on how to setup a monitoring session, refer to Section 2.1, “Uncore Per-Socket
Performance Monitoring Control”
.
2.6.3 IRP Performance Monitors
Table 2-105. IRP Performance Monitoring Registers
Table 2-104. Unit Masks for WR_CAS_RANK7
Extension
umask
[15:8]
Description
BANK0 bxxxxxxx1 Bank 0
BANK1 bxxxxxx1x Bank 1
BANK2 bxxxxx1xx Bank 2
BANK3 bxxxx1xxx Bank 3
BANK4 bxxx1xxxx Bank 4
BANK5 bxx1xxxxx Bank 5
BANK6 bx1xxxxxx Bank 6
BANK7 b1xxxxxxx Bank 7
Register Name
PCICFG
Address
Size
(bits)
Description
PCICFG Base Address Dev:Func
IRP PMON Registers D5:F6
Box-Level Control/Status
IRP_PCI_PMON_BOX_STATUS F8 32 IRP PMON Box-Wide Status
IRP_PCI_PMON_BOX_CTL F4 32 IRP PMON Box-Wide Control
Generic Counter Control
IRP1_PCI_PMON_CTL1 E4 32 IRP 1 PMON Control for Counter 1
IRP1_PCI_PMON_CTL0 E0 32 IRP 1 PMON Control for Counter 0
IRP0_PCI_PMON_CTL1 DC 32 IRP 0 PMON Control for Counter 1
IRP0_PCI_PMON_CTL0 D8 32 IRP 0 PMON Control for Counter 0