Uncore Manual

Reference Number: 329468-002 101
Uncore Performance Monitoring
IRP Performance Monitoring
Table 2-108. IRP_PCI_PMON_CTL{3-0} Register – Field Definitions
If accessible, software can continuously read the data registers without disabling event collection.
Table 2-109. IRP{0,1}_PCI_PMON_CTR{1-0} Register – Field Definitions
2.6.4 IRP Performance Monitoring Events
2.6.4.1 An Overview
IRP provides events to track information related to all the traffic passing through it’s boundaries.
• Write Cache Occupancy
• Ingress/Egress Traffic - by Ring Type
• Stalls awaiting Credits
2.6.5 IRP Box Events Ordered By Code
The following table summarizes the directly measured IRP Box events.
Field Bits Attr
HW
Reset
Val
Description
thresh 31:24 RW-V 0 Threshold used in counter comparison.
rsv 23 RV 0 Reserved. SW must write to 0 else behavior is undefined.
en 22 RW-V 0 Local Counter Enable.
rsv 21:20 RV 0 Reserved. SW must write to 0 else behavior is undefined.
ig 19 RV 0 Ignored
edge_det 18 RW-V 0 When set to 1, rather than measuring the event in each
cycle it is active, the corresponding counter will increment
when a 0 to 1 transition (i.e. rising edge) is detected.
When 0, the counter will increment in each cycle that the
event is asserted.
NOTE: .edge_det is in series following .thresh. Due to this,
the .thresh field must be set to a non-0 value. For events
that increment by no more than 1 per cycle, set .thresh to
0x1.
rst 17 WO 0 When set to 1, the corresponding counter will be cleared to
0.
rsv 16 RV 0 Reserved. SW must write to 0 else behavior is undefined.
umask 15:8 RW-V 0 Select subevents to be counted within the selected event.
ev_sel 7:0 RW-V 0 Select event to be counted.
Field Bits Attr
HW
Reset
Val
Description
ig 63:44 RV 0 Ignored
event_count 43:0 RW-V 0 44-bit performance event counter