Uncore Manual

Reference Number: 329468-002 109
Uncore Performance Monitoring
Power Control (PCU) Performance Monitoring
TxR_REQUEST_OCCUPANCY
• Title: Outbound Request Queue Occupancy
• Category: OUTBOUND_REQUESTS Events
• Event Code: 0x0d
• Max. Inc/Cyc:. 1, Register Restrictions: 0-1
• Definition: Accumulates the number of outstanding outbound requests from the IRP to the
switch (towards the devices). This can be used in conjunction with the allocations event in order
to calculate average latency of outbound requests.
WRITE_ORDERING_STALL_CYCLES
• Title: Write Ordering Stalls
• Category: STALL_CYCLES Events
• Event Code: 0x1a
• Max. Inc/Cyc:. 1, Register Restrictions: 0-1
• Definition: Counts the number of cycles when there are pending write ACK's in the switch but
the switch->IRP pipeline is not utilized.
2.7 POWER CONTROL (PCU) PERFORMANCE MONITORING
2.7.1 Overview of the PCU
The PCU is the primary Power Controller for the physical processor package.
The uncore implements a power control unit acting as a core/uncore power and thermal manager. It
runs its firmware on an internal micro-controller and coordinates the socket’s power states.
The PCU algorithmically governs the P-state of the processor, C-state of the core and the package C-
state of the socket. It also enables the core to go to a higher performance state (“turbo mode”) when
the proper set of conditions are met. Conversely, the PCU will throttle the processor to a lower perfor-
mance state when a thermal violation occurs.
Through specific events, the OS and the PCU will either promote or demote the C-State of each core
by altering the voltage and frequency. The system power state (S-state) of all the sockets in the
system is managed by the server legacy bridge in coordination with all socket PCUs.
The PCU communicates to all the other units through multiple PMLink interfaces on-die and Message
Channel to access their registers. The OS and BIOS communicates to the PCU thru standardized MSR
registers and ACPI.
The PCU also acts as the interface to external management controllers via PECI and voltage regula-
tors (NPTM). The DMI interface is the communication path from the southbridge for system power
management.
NOTE
Many power saving features are tracked as events in their respective units. For
example, Intel
®
QPI Link Power saving states and Memory CKE statistics are captured
in the Intel
®
QPI Perfmon and iMC Perfmon respectively.
2.7.2 PCU Performance Monitoring Overview
The uncore PCU supports event monitoring through four 48-bit wide counters
(PCU_MSR_PMON_CTR{3:0}). Each of these counters can be programmed