Uncore Manual

Uncore Performance Monitoring
Power Control (PCU) Performance Monitoring
110 Reference Number: 329468-002
(PCU_MSR_PMON_CTL{3:0}) to monitor any PCU event. The PCU counters can increment by a
maximum of 4b per cycle.
Two extra 64-bit counters are also provided by the PCU to track C-State Residence. Although docu-
mented in this manual for reference, these counters exist outside of the PMON infrastructure.
For information on how to setup a monitoring session, refer to Section 2.1, “Uncore Per-Socket Perfor-
mance Monitoring Control”
.
2.7.2.1 PCU PMON Registers - On Overflow and the Consequences (PMI/Freeze)
If an overflow is detected from a PCU performance counter enabled to communicate its overflow
(PCU_MSR_PMON_CTL.ov_en is set to 1), the overflow bit is set at the box level
(PCU_MSR_PMON_BOX_STATUS.ov) and an overflow message is sent to the UBox. When the UBox
receives the overflow signal, the U_MSR_PMON_GLOBAL_STATUS.ov_p bit is set (see Table 2-3,
“U_MSR_PMON_GLOBAL_STATUS Register – Field Definitions”) and a PMI can be generated.
Once a freeze has occurred, in order to see a new freeze, the overflow field responsible for the freeze,
must be cleared by setting the corresponding bit in PCU_MSR_PMON_BOX_STATUS.ov and
U_MSR_PMON_GLOBAL_STATUs.ov_p to 0. Assuming all the counters have been locally enabled (.en
bit in control registers meant to monitor events) and the overflow bit(s) has been cleared, the PCU is
prepared for a new sample interval. Once the global controls have been re-enabled (Section 2.1.4,
“Enabling a New Sample Interval from Frozen Counters”), counting will resume.
2.7.3 PCU Performance Monitors
Table 2-118. PCU Performance Monitoring MSRs
MSR Name
MSR
Address
Size
(bits)
Description
Generic Counters
PCU_MSR_PMON_CTR3 0x0C39 64 PCU PMON Counter 3
PCU_MSR_PMON_CTR2 0x0C38 64 PCU PMON Counter 2
PCU_MSR_PMON_CTR1 0x0C37 64 PCU PMON Counter 1
PCU_MSR_PMON_CTR0 0x0C36 64 PCU PMON Counter 0
Box-Level Filter
PCU_MSR_PMON_BOX_FILTER 0x0C34 32 PCU PMON Filter
Generic Counter Control
PCU_MSR_PMON_CTL3 0x0C33 32 PCU PMON Control for Counter 3
PCU_MSR_PMON_CTL2 0x0C32 32 PCU PMON Control for Counter 2
PCU_MSR_PMON_CTL1 0x0C31 32 PCU PMON Control for Counter 1
PCU_MSR_PMON_CTL0 0x0C30 32 PCU PMON Control for Counter 0
Box-Level Control/Status
PCU_MSR_PMON_BOX_STATUS 0x0C35 32 PCU PMON Box-Wide Status
PCU_MSR_PMON_BOX_CTL 0x0C24 32 PCU PMON Box-Wide Control
Fixed (Non-PMON) Counters
PCU_MSR_CORE_C6_CTR 0x03FD 64 Fixed C-State Residency Counter
PCU_MSR_CORE_C3_CTR 0x03FC 64 Fixed C-State Residency Counter