Uncore Manual

Reference Number: 329468-002 111
Uncore Performance Monitoring
Power Control (PCU) Performance Monitoring
2.7.3.1 PCU Box Level PMON State
The following registers represent the state governing all box-level PMUs in the PCU.
In the case of the PCU, the PCU_MSR_PMON_BOX_CTL register provides the ability to manually
freeze the counters in the box (.frz) and reset the generic state (.rst_ctrs and .rst_ctrl).
The PCU provides two extra MSRs that provide additional static performance information to software
but exist outside of the PMON infrastructure (e.g. they can’t be frozen or reset). They are included for
the convenience of software developers need to efficiently access this data.
If an overflow is detected from one of the PCU PMON registers, the corresponding bit in the
PCU_MSR_PMON_BOX_STATUS.ov field will be set. To reset these overflow bits, a user must write a
value of ‘1’ to them (which will clear the bits).
Table 2-119. PCU_MSR_PMON_BOX_CTL Register – Field Definitions
U
Table 2-120. PCU_MSR_PMON_BOX_STATUS Register – Field Definitions
2.7.3.2 PCU PMON state - Counter/Control Pairs
The following table defines the layout of the PCU performance monitor control registers. The main
task of these configuration registers is to select the event to be monitored by their respective data
counter (.ev_sel, .umask). Additional control bits are provided to shape the incoming events (e.g.
.edge_det, .thresh) as well as provide additional functionality for monitoring software (.rst,.ov_en).
Due to the fact that much of the PCU’s functionality is provided by an embedded microcontroller,
many of the available events are generated by the microcontroller and handed off to the hardware for
capture by the PMON registers. Among the events generated by the microcontroller are occupancy
events allowing a user to measure the number of cores in a given C-state per-cycle. Given this unique
situation, extra control bits are provided to filter the output of the these special occupancy events.
Field Bits Attr
HW
Reset
Val
Description
rsv 31:18 RV 0 Reserved
rsv 17:16 RV 0 Reserved; SW must write to 1 else behavior is undefined.
rsv 15:9 RV 0 Reserved
frz 8 WO 0 Freeze.
If set to 1 the counters in this box will be frozen.
rsv 7:2 RV 0 Reserved
rst_ctrs 1 WO 0 Reset Counters.
When set to 1, the Counter Registers will be reset to 0.
rst_ctrl 0 WO 0 Reset Control.
When set to 1, the Counter Control Registers will be reset to
0.
Field Bits Attr
HW
Reset
Val
Description
rsv 31:4 RV 0 Reserved
ov 3:0 RW1C 0 If an overflow is detected from the corresponding
PCU_MSR_PMON_CTR register, it’s overflow bit will be set.
NOTE: Write of ‘1’ will clear the bit.