Uncore Manual

Uncore Performance Monitoring
Power Control (PCU) Performance Monitoring
114 Reference Number: 329468-002
Table 2-123. PCU_MSR_PMON_BOX_FILTER Register – Field Definitions
The PCU includes two extra MSRs that track the number of cycles a core (any core) is in either the C3
or C6 state. As mentioned before, these counters are not part of the PMON infrastructure so they can’t
be frozen or reset with the otherwise controlled by the PCU PMON control registers.
NOTE
To be clear, these counters track the number of cycles some core is in C3/6 state. It
does not track the total number of cores in the C3/6 state in any cycle. For that, a user
should refer to the regular PCU event list.
Table 2-124. PCU_MSR_CORE_C6_CTR Register – Field Definitions
Table 2-125. PCU_MSR_CORE_C3_CTR Register – Field Definitions
2.7.4 PCU Performance Monitoring Events
2.7.4.1 An Overview:
The PCU provides the ability to capture information covering a wide range of the PCU’s functionality
including:
• Number of cores in a given C-state per-cycle
• Core State Transitions - there are a larger number of events provided to track when cores
transition C-state, when the enter/exit specific C-states, when they receive a C-state demotion,
etc.
• Package State Transitions
• Frequency/Voltage Banding - ability to measure the number of cycles the uncore was operating
within a frequency or voltage ‘band’ that can be specified in a separate filter register.
Field Bits Attr
HW
Reset
Val
Description
rsv 63:48 RV 0 Reserved
filt31_24 31:24 RW-V 0 Band 3 - For Voltage/Frequency Band Event
filt23_16 23:16 RW-V 0 Band 2 - For Voltage/Frequency Band Event
filt15_8 15:8 RW-V 0 Band 1 - For Voltage/Frequency Band Event
filt7_0 7:0 RW-V 0 Band 0 - For Voltage/Frequency Band Event
Field Bits Attr
HW
Reset
Val
Description
event_count 63:0 RW-V 0 64-bit performance event counter
Field Bits Attr
HW
Reset
Val
Description
event_count 63:0 RW-V 0 64-bit performance event counter