Uncore Manual

Reference Number: 329468-002 7
Introduction
Figure 1-3.Intel Xeon Processor E5-1600 v2 Product Family Block Diagram
NOTE
This diagram represents one possible EN configuration. Not all skus support all
features.
1.2 UNCORE PMON OVERVIEW
The uncore performance monitoring facilities are organized into per-component performance moni-
toring (or ‘PMON’) units. A PMON unit within an uncore component may contain one of more sets of
counter registers. With the exception of the UBox, each PMON unit provides a unit-level control register
to synchronize actions across the counters within the box (e.g. to start/stop counting).
Events can be collected by reading a set of local counter registers. Each counter register is paired with
a dedicated control register used to specify what to count (i.e. through the event select/umask fields)
and how to count it. Some units provide the ability to specify additional information that can be used to
‘filter’ the monitored events (e.g., C-box; see Section 2.3.3.3, “CBo Filter Registers
(Cn_MSR_PMON_BOX_FILTER{0,1})”).
Each of these boxes communicates with the U-Box which contains registers to control all uncore PMU
activity (as outlined in Section 2.1, “Uncore Per-Socket Performance Monitoring Control”). Uncore
performance monitors represent a per-socket resource that is not meant to be affected by context