Uncore Manual

Uncore Performance Monitoring
Intel® QPI Link Layer Performance Monitoring
132 Reference Number: 329468-002
U_MSR_PMON_GLOBAL_STATU.ov_q. Assuming all the counters have been locally enabled (.en bit in
data registers meant to monitor events) and the overflow bit(s) has been cleared, the QPI Port is
prepared for a new sample interval. Once the global controls have been re-enabled (Section 2.1.4,
“Enabling a New Sample Interval from Frozen Counters”), counting will resume.
2.8.3 Intel® QPI Performance Monitors
Table 2-128. Intel® QPI Performance Monitoring Registers
Register Name
PCICFG
Address
Size
(bits)
Description
PCICFG Base Address Dev:Func
QPI0 Port 0 PMON Registers D8:F2
QPI0 Port 1 PMON Registers D9:F2
QPI1 Port 2 PMON Registers D24:F2
Box-Level Control/Status
Q_Py_PCI_PMON_BOX_STATUS F8 32 QPI Port y PMON Box-Wide Status
Q_Py_PCI_PMON_BOX_CTL F4 32 QPI Port y PMON Box-Wide Control
Generic Counter Control
Q_Py_PCI_PMON_CTL3 E4 32 QPI Port y PMON Control for Counter 3
Q_Py_PCI_PMON_CTL2 E0 32 QPI Port y PMON Control for Counter 2
Q_Py_PCI_PMON_CTL1 DC 32 QPI Port y PMON Control for Counter 1
Q_Py_PCI_PMON_CTL0 D8 32 QPI Port y PMON Control for Counter 0
Generic Counters
Q_Py_PCI_PMON_CTR3 BC+B8 32x2 QPI Port y PMON Counter 3
Q_Py_PCI_PMON_CTR2 B4+B0 32x2 QPI Port y PMON Counter 2
Q_Py_PCI_PMON_CTR1 AC+A8 32x2 QPI Port y PMON Counter 1
Q_Py_PCI_PMON_CTR0 A4+A0 32x2 QPI Port y PMON Counter 0
QPI0 Mask/Match Port 0 PMON Registers D8:F6
QPI0 Mask/Match Port 1 PMON Registers D9:F6
QPI1 Mask/Match Port 2 PMON Registers D24:F6
Box-Level Filters
Q_Py_PCI_PMON_PKT_MASK1 23C 32 QPI Port y PMON Packet Filter Mask 1
Q_Py_PCI_PMON_PKT_MASK0 238 32 QPI Port y PMON Packet Filter Mask 0
Q_Py_PCI_PMON_PKT_MATCH1 22C 32 QPI Port y PMON Packet Filter Match 1
Q_Py_PCI_PMON_PKT_MATCH0 228 32 QPI Port y PMON Packet Filter Mask 0
QPI0 Misc Register Port 0,1 D8:F0
QPI1 Misc Register Port 2 D24:F0
Misc (Non-PMON) Counters
QPI_RATE_STATUS 0xD4 32 QPI Rate Status