Uncore Manual

Reference Number: 329468-002 163
Uncore Performance Monitoring
R2PCIe Performance Monitoring
VNA_CREDIT_RETURNS
• Title: VNA Credits Returned
• Category: VNA_CREDIT_RETURN Events
• Event Code: 0x1c
• Extra Select Bit: Y
• Max. Inc/Cyc:. 1, Register Restrictions: 0-3
• Definition: Number of VNA credits returned.
VNA_CREDIT_RETURN_OCCUPANCY
• Title: VNA Credits Pending Return - Occupancy
• Category: VNA_CREDIT_RETURN Events
• Event Code: 0x1b
• Extra Select Bit: Y
• Max. Inc/Cyc:. 128, Register Restrictions: 0-3
• Definition: Number of VNA credits in the Rx side that are waiting to be returned back across the
link.
2.9 R2PCIE PERFORMANCE MONITORING
2.9.1 Overview of the R2PCIe Box
R2PCIe represents the interface between the Ring and IIO traffic to/from PCIe.
2.9.2 R2PCIe Performance Monitoring Overview
The R2PCIe Box supports event monitoring through four 44b wide counters (R2_PCI_PMON_CTR/
CTL{3:0}). Each of these four counters can be programmed to count almost any R2PCIe event (see
NOTE for exceptions). the R2PCIe counters can increment by a maximum of 5b per cycle.
For information on how to setup a monitoring session, refer to Section 2.1, “Uncore Per-Socket
Performance Monitoring Control”
.
NOTE
Only counter 0 can be used for tracking occupancy events. Only counters 2&3 can be
used for ring utilization events.
2.9.2.1 R2PCIe PMON Registers - On Overflow and the Consequences (PMI/Freeze)
If an overflow is detected from an R2PCIe performance counter enabled to communicate its overflow
(R2_PCI_PMON_CTL.ov_en is set to 1), the overflow bit is set at the box level
(R2_PCI_PMON_BOX_STATUS.ov) and an overflow message is sent to the UBox. When the UBox
receives the overflow signal, U_MSR_PMON_GLOBAL_STATUS.ov_rp is set (see Table 2-3,
“U_MSR_PMON_GLOBAL_STATUS Register – Field Definitions”) and a PMI can be generated.
Once a freeze has occurred, in order to see a new freeze, the overflow field responsible for the freeze,
must be cleared by setting the corresponding bit in R2_PCI_PMON_BOX_STATUS.ov and
U_MSR_PMON_GLOBAL_STATU.ov_rp. Assuming all the counters have been locally enabled (.en bit
in data registers meant to monitor events) and the overflow bit(s) has been cleared, the R2PCIe Link
is prepared for a new sample interval. Once the global controls have been re-enabled (Section 2.1.4,
“Enabling a New Sample Interval from Frozen Counters”), counting will resume.