Uncore Manual

Uncore Performance Monitoring
R2PCIe Performance Monitoring
164 Reference Number: 329468-002
2.9.3 R2PCIe Performance Monitors
Table 2-172. R2PCIe Performance Monitoring Registers
2.9.3.1 R2PCIe Box Level PMON State
The following registers represent the state governing all box-level PMUs in the R2PCIe Box.
In the case of the R2PCIe, the R2_PCI_PMON_BOX_CTL register provides the ability to manually freeze
the counters in the box (.frz) and reset the generic state (.rst_ctrs and .rst_ctrl).
If an overflow is detected from one of the R2PCIe PMON registers, the corresponding bit in the
R2_PCI_PMON_BOX_STATUS.ov field will be set. To reset these overflow bits, a user must write a value
of ‘1’ to them (which will clear the bits).
Table 2-173. R2_PCI_PMON_BOX_CTL Register – Field Definitions
U
Register Name
PCICFG
Address
Size
(bits)
Description
PCICFG Base Address Dev:Func
R2PCIe PMON Registers D19:F1
Box-Level Control/Status
R2_PCI_PMON_BOX_STATUS F8 32 R2PCIe PMON Box-Wide Status
R2_PCI_PMON_BOX_CTL F4 32 R2PCIe PMON Box-Wide Control
Generic Counter Control
R2_PCI_PMON_CTL3 E4 32 R2PCIe PMON Control for Counter 3
R2_PCI_PMON_CTL2 E0 32 R2PCIe PMON Control for Counter 2
R2_PCI_PMON_CTL1 DC 32 R2PCIe PMON Control for Counter 1
R2_PCI_PMON_CTL0 D8 32 R2PCIe PMON Control for Counter 0
Generic Counters
R2_PCI_PMON_CTR3 BC+B8 32x2 R2PCIe PMON Counter 3
R2_PCI_PMON_CTR2 B4+B0 32x2 R2PCIe PMON Counter 2
R2_PCI_PMON_CTR1 AC+A8 32x2 R2PCIe PMON Counter 1
R2_PCI_PMON_CTR0 A4+A0 32x2 R2PCIe PMON Counter 0
Field Bits Attr
HW
Reset
Val
Description
ig 31:9 RV 0 Ignored
frz 8 WO 0 Freeze.
If set to 1 the counters in this box will be frozen.
ig 7:2 RV 0 Ignored
rst_ctrs 1 WO 0 Reset Counters.
When set to 1, the Counter Registers will be reset to 0.
rst_ctrl 0 WO 0 Reset Control.
When set to 1, the Counter Control Registers will be reset to
0.