Uncore Manual

Reference Number: 329468-002 165
Uncore Performance Monitoring
R2PCIe Performance Monitoring
Table 2-174. R2_PCI_PMON_BOX_STATUS Register – Field Definitions
2.9.3.2 R2PCIe PMON state - Counter/Control Pairs
The following table defines the layout of the R2PCIe performance monitor control registers. The main
task of these configuration registers is to select the event to be monitored by their respective data
counter (.ev_sel, .umask). Additional control bits are provided to shape the incoming events (e.g.
.edge_det, .thresh) as well as provide additional functionality for monitoring software (.rst,.ov_en).
Table 2-175. R2_PCI_PMON_CTL{3-0} Register – Field Definitions
The R2PCIe performance monitor data registers are 44-bit wide. A counter overflow occurs when a
carry out from bit 43 is detected. Software can force all uncore counting to freeze after N events by
preloading a monitor with a count value of 2
44
- N and setting the control register to send an overflow
message to the UBox (Section 2.1.1.1, “Freezing on Counter Overflow”). During the interval of time
between overflow and global disable, the counter value will wrap and continue to collect events.
If accessible, software can continuously read the data registers without disabling event collection.
Field Bits Attr
HW
Reset
Val
Description
ig 31:4 RV 0 Ignored
ov 3:0 RW1C 0 If an overflow is detected from the corresponding
R2_PCI_PMON_CTR register, it’s overflow bit will be set.
NOTE: Write of ‘1’ will clear the bit.
Field Bits Attr
HW
Reset
Val
Description
thresh 31:24 RW-V 0 Threshold used in counter comparison.
rsv 23 RV 0 Reserved. SW must write to 0 else behavior is undefined.
en 22 RW-V 0 Local Counter Enable.
rsv 21 RV 0 Reserved. SW must write to 0 else behavior is undefined.
ov_en 20 RW-V 0 When this bit is asserted and the corresponding counter
overflows, its overflow bit is set in the local status register
(R2_PCI_PMON_BOX_STATUS.ov) and an overflow is sent
on the message channel to the UBox. When the overflow is
received by the UBox, the bit corresponding to this R2 will
be set in U_MSR_PMON_GLOBAL_STATUS.ov_rp.
ig 19 RV 0 Ignored
edge_det 18 RW-V 0 When set to 1, rather than measuring the event in each
cycle it is active, the corresponding counter will increment
when a 0 to 1 transition (i.e. rising edge) is detected.
When 0, the counter will increment in each cycle that the
event is asserted.
NOTE: .edge_det is in series following .thresh. Due to this,
the .thresh field must be set to a non-0 value. For events
that increment by no more than 1 per cycle, set .thresh to
0x1.
rst 17 WO 0 When set to 1, the corresponding counter will be cleared to
0.
rsv 16 RV 0 Reserved. SW must write to 0 else behavior is undefined.
umask 15:8 RW-V 0 Select subevents to be counted within the selected event.
ev_sel 7:0 RW-V 0 Select event to be counted.